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Comments:
<0> It's because I'm coding in ASM for GCC...
<0> in accepts intel syntax, but I still need those "%"
<0> s/in/it/
<1> Axioplase: ah, so gcc intel syntax has %, okay
<1> though from what I gather you should present stuff to this "high level language guy 2" only in the most familiar syntax possible
<0> yeah...
<2> Maybe it's me, but how to you get to where you're asking that question? Any ***embler reference for the x86 will show 'add <reg1>,<reg2> -- add <reg1> and <reg2> and leave the result in <reg1>', or words to that effect.
<0> lea ebx, (var1 + var2) should be good too I think...
<3> some image processing experts there?
<4> Do all memory accesses go through the virtual memory system on modern processors?
<5> in modern oses, yeah.
<5> if theres ans MMU...
<3> are some image processing users there?
<4> pireau: register accesses too, right?
<5> registers arent'n in the main ram...
<2> no, register access access registers.
<2> throw an extra 'es' in ther as appropriate.
<1> fasta: register accesses aren't memory accesses ;)
<4> Ok, so when a different process is run, the registers are copied to main memory, and copied back when the process is setup to run again.
<1> yep
<1> that's called a "context switch"
<4> oggis_: yeah, it makes sense.
<4> So, it boils down to 1) memory accesses consisting of the caches + main memory + memory represented on harddisk (represented by the virtual memory system) and registers.
<4> add an extra 2) there
<2> And processor cache.
<4> You mean L1 and L2 cache?
<1> that is there, and by the way you don't really have to count it separately from main memory, since it's not exclusive
<1> so everything that is in caches is also in RAM
<2> It's not exclusive, but if you're wondering how all the pieces work, and what goes through where, they're part of the picture.
<4> When you speak of cache, you mean processor cache?
<2> Right.
<4> In this setup it seems that in a context switch the cache must be invalidated.
<4> Never mind
<4> I don't understand why processor caches are not part of the virtual memory system. I.e. that they are not checked. To me it seems that you would read-only caches for that to work.
<2> Virtual memory is a construct of the OS, not part of the CPU & memory itself.
<4> Quartus: but doesn't the CPU implement most of the virtual memory system already?
<2> No. It's an OS construct.
<5> well, there's paging and segmentation
<2> Yes. Nothing particularly virtual about either one.
<5> with page tables and page directories
<4> Yes, I meant those.
<5> yeah
<5> but in a VM environment, the OS makes them work.
<4> You mean something like Xen?
<2> Xen is for virtual machines, which are something else again.
<4> oh, right Virtual Memory, sorry
<0> er.. how to debug asm with gdb ? though I compile (with gcc) with "-g" when i gdb the binary, I can't lsit the source code...
<0> 1 ../sysdeps/i386/elf/start.S: No such file or directory.
<4> What does a CLOCK page replacement policy?
<4> It should be something like other cache policies like Most Recently Used, etc.
<2> on x86, which is faster: xor ax, ax mov.b ax,#1 or mov.l ax, #1 ?
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