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Comments:
<0> markos_64: it was just painful getting there i know
<1> seb-: not entirely true. there is special instruction called LEA, which does weird things to [] thingies.
<1> seb-: other than that, right.
<2> markos_64: i knew about s390
<2> but not the others
<3> you a s390 coder?
<2> nop
<1> ok, about the psABI-arm you're looking at now, it doesn't specify the call conventions, as opposed to most other psABIs
<1> but the document you're looking for is at http://www.heyrick.co.uk/***embler/apcsintro.html
<1> well, this isn't exactly the standard, but it documents basic parameter p***ing anyway
<1> just uploaded the real standard to http://x-os.homeip.net/x-os/hdir/pdf/sysv/psABI-arm-call.pdf. enjoy.
<2> markos_64: thanks a bunch
<2> i'll prolly wget that folder
<0> lea can be replaced with a mov and an add right?
<2> yeah
<0> pireau: cuz you can't do mov eax, ebp-4
<0> only mov eax, ebp ; sub eax, 4
<3> righty.
<3> the fun fact is that mov a, b is exactly equivalent to lea a, [b]
<3> but lea is more powerful, since you can make use of all kind of calculations in []
<4> Hi! I have some beginner questions about ***embly [produced by IDA Pro dis***embler], if any of you would be so kind and awnser those questions, I would be much appreciative. The questions with some sample code are located at http://rafb.net/paste/results/ef2LTk39.html
<5> learn asm
<4> edcba: well.. as there are way too many "tutorials" on the net, that actually only teach you the basic functionality (mov, call, jmp, etc), it is really hard to actually find those tutorials that cover those basis that I'm struggling, and that's why I'm asking the question here.
<5> http://www.xs4all.nl/~smit/asm01001.htm
<4> edcba: thanks
<2> hello
<6> is there a site someone would recommend for sse and mmx instruction reference?
<2> the "IA-32 Intel Architecture Software Developer's Manual; Volume 2"
<2> should be available in PDF @ intel..
<6> thanks pireau
<2> I got a dead-tree copy of the three volumes here
<2> they're a good reference
<6> pireau: I don't suppose you know if gcc takes advantage well or not?
<6> pireau: is it worthwhile to write inline asm usually I guess is what I'm asking
<2> gcc does great optimisations on x86
<2> you could check if it uses the sse and mmx registers
<2> i never checked.
<6> pireau: I'll keep that in mind then
<6> I believe it does if you tell it to
<2> if gcc doesn't; it wouldn't hurt recode parts in asm.
<6> wow, I didn't realize there were this many instructions for x86
<2> BrigadierFrog: :)
<7> morning
<8> no.
<7> :)
<9> Why do some people use "xor %eax,%eax" (an example) instead of "mov %eax,0" ?
<10> sybec, Less bytes
<9> thanks
<10> No null bytes also. Perhaps that doesn't matter to most people
<11> hello
<1> hi
<11> i am here to learn asm
<11> i want to know if asm is stil used heavily nowadays
<8> alexi5: not really, no.
<3> it isn't.
<8> alexi5, on the other hand, if you want to understand whats going on, or if you want something that sets you apart from the 50000 other job applicants, its worth learning imo
<11> ok
<11> i did some as on a motorola 6800
<8> which means that learning will be much, much easier
<11> yeah
<11> the the x86 architecture has less registers
<3> and ****s much more, too.
<8> yeah the x86 architecutre isn't fun
<12> well, I think, learning how to setup your email system is damn much harder than x86 architecture.
<12> :)
<8> I tend to agree
<8> I just said that it definately had its "not fun" parts
<8> but for normal stuff its just fine
<12> Instruction format is quite twisted, thought it has cool instructions.
<8> oh comon its not that bad when you get to know it
<8> its system programming instructions are a bit hard to understand though
<12> billfur: you mean the stuff which is used to prevent programs from hammering the kernel to pieces?
<8> yeah
<8> well I mean getting your head around the way code segments fit into the picture
<8> (not paging)
<12> I've been wondering that.
<12> How does kernel prevents it?
<8> Oh, my understanding is that the page table has flags that can be checked on writing and if the CPL is less then the level on the memory it won't allow it
<8> err is more then
<8> (roughly speaking)
<8> I was more talking about cs/ds/etc
<8> but, I'll defer a good answer to someones whos finished reading chapter 3 which I'm just starting =p
<3> yawn.
<8> like mwk
<12> Aah.
<3> there is this little thing called paging
<3> which means whole virtual memory space is divided into pages
<3> which can be arbitrarily mapped into physical space
<3> providing for virtual memory, shared memory segments, and all sorts of good stuff
<3> also, each page has some flags
<3> one of them is user/kernel flag
<3> if it isn't set, you cannot do anything with this page if you aren't the Kernel.
<3> and since kernel will only give you access to pages it thinks are reasonable, you're stuck in your closed memory space. no way to hurt kernel. or other programs.
<3> [only kernel can change the page tables]
<3> and whether you're kernel or not is determined by Code Priviledge Level of code segment you're currently executing
<12> How does it keep care from registers? Or are every register loaded into memory and moved from there between processes executing?
<3> code segment changes are all secured up so that you can only go to kernel mode by using a special syscall instruction. and it always goes to pre-defined place.
<3> each thread has its own registers.
<3> when kernel switches threads, it swaps real register set with image in memory.
<12> And only code segments are secured up by kernel...
<12> argh
<12> no kernel.
<12> mwk: It seems that works generally well.
<8> mwk: whats the point of codesegments on 32 bit mode?
<8> or more specifically the cs register
<3> 1. intel didn't want to lose face over doing the original brain-damaged thing, so continued to support segments on 32bit
<8> so for all pratical purposes set them to 0.
<3> 2. specifically, segmentation is needed for code segment, since it has its Code Priviledge Level determined from the segment. and this is used to distingush kernel from user mode.
<3> for all practical purposes, make 4 descriptors with base 0 and length 4GB. [user code, user data, kernel code, kernel data].
<8> 64 bit mode goes ahead and does that, how does it distinguish kernel from user?
<12> mwk: what user code and user data overlap?
<12> s/what/can
<8> yeah segmenets can overlap
<8> just think of them as offsets added to certain instructions
<8> in 32 bit land atleast
<12> well, can you write into code segment as well?
<8> yes.
<3> billfur: code segment IS used. but in highly reduced form. namely, onlt CPL remains.
<3> no.
<8> ah
<3> you cannot write to code segment.
<3> but you can write to data segment which references the same space as your code segment.
<12> fs gs es ss cs ds ... there are six segment registers, if you use two for kernel and two for user program, where do you use the last two?
<3> wrong, wrong, wrong.
<3> there are six segments register.
<3> and there are four segments
<3> but two segment registers can point to same segment.
<3> in use code, cs points to user code; ds, es, ss point to user data segment; fs and gs are unused.
<3> in kernel code, cs points to kernel code; ds, es, ss point to kernel data segment; fs and gs are unused.
<3> well, actually, gs or fs are commonly used for thread-local storage in user space.
<8> ah so thats how its implemented
<12> oh.
<8> (thread local storage that is)
<12> do you mean gs or fs could be used for implementing co-operative threads inside a process?
<3> http://x-os.homeip.net/x-os/hdir/pdf/elf/tls.pdf
<3> this thing describes how it works on 'nix systems
<3> Cheery: no. some languages/OSes/whatever have a term Thread-Local Storage. which means you can have a variable, sorta like global, but global only inside a single thread. meaning that each thread has its own version of it. fs/gs can be used to point to per-thread block of such variables.
<13> helo
<14> ne /msg _axa_ blah - anally retentive opers abound in #gentoo
<15> "anally retentive"? does that mean you don't poop? :)
<16> or nor often enough therefore producing arse splitting tree trunks
<16> nor=not
<13> what does 'rep stosd' in nasm?
<16> nasm has nothing to do with it, its standard intel syntax see intel manual
<0> just checking...*math* outside of []'s always bad right?...i.e. 'mov ebx, [eax+4]' goot but 'mov eax, edx+4' BAD right?
<0> s/goot/good
<0> must do==> add edx,4 ; mov eax, edx right?
<0> little endianness bites you when in C when you try to typecast something to an int.....WHEN does little endianness show up in asm?
<12> sebbbi?
<17> seb- : Well, one time is when you try to typecast something to an int.
<17> When you use what used to be a series of bytes as a dword, for instance.
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